1. Field of the Invention
The present invention relates to synchronizing devices, and particularly to improvement for eliminating the necessity for the FIFO required in a conventional device to realize size reduction of the device.
2. Description of the Background Art
FIG. 40 is a block diagram showing the structure of a conventional synchronizing device as a background of the present invention. This device 150) converts an input data signal Data.sub.-- In formed of a sequence of 1-bit-long unit data into an output data signal Data.sub.-- Out formed of a sequence of L-bit-long unit data. The device 150 includes a synchronization control portion 151, L-bit shift registers 152 and 154, a FIFO 153, and comparators 155 and 156.
The 1-bit-long unit data forming the input data signal Data.sub.-- In is inputted to the L-bit shift register 152 in synchronization with the pulse of a clock signal Clk (i.e., for each clock cycle). The L-bit shift register 152 always holds L unit data inputted in a period of L clock cycles from the present to the past. That is to say, the L-bit shift register 152 corresponds to a serial-parallel converting device for converting serial data into parallel data.
The oldest unit data in the L unit data held in the L-bit shift register 152 is sent to the FIFO 153 in each clock cycle. It is assumed in the description below that the output data signal Data.sub.-- Out is a data signal based on the MPEG standard, or a data signal formed of unit packets each including a sequence of 204 pieces of 8-bit-long unit data.
In this case, the FIFO 153 has a storage capacity of 8.times.204 bits. Accordingly, the unit data inputted to the FIFO 153 is outputted after 8.times.204 clock cycles. The 1-bit-long unit data passed through the FIFO 153 is inputted to the L-bit shift register 154 for each clock cycle. The L-bit shift register 154 is formed identically to the L-bit shift register 152.
The synchronization control portion 151 is a device portion which functions to control operations of the comparators 155, 156, etc. The synchronization control portion 151 is fed with an L-bit-long synchronizing code Cd indicating a head word of a packet. The comparator 155 compares the value of the synchronizing code Cd sent from the synchronization control portion 151 and the L-bit data held in the L-bit shift register 152. Similarly, the comparator 156 compares the value of the synchronizing code Cd sent from the synchronization control portion 151 and the L-bit data held in the L-bit shift register 154.
When the comparators 155 and 156 detect that the L-bit data in the L-bit shift register 152 and the L-bit data in the L-bit shift register 154 simultaneously coincide with the synchronizing code Cd, the synchronization control portion 151 recognizes the synchronizing code Cd as the head word of the packet. Then the sequence of the 1-bit-long unit data is separated by L bits, following after the L-bit-long head word. As a result, L-bit-long unit data is outputted as the output data signal Data.sub.-- Out. This is realized as the synchronization control portion 151 causes the L-bit data held in the L-bit shift register 154 to be outputted as the output data signal Data.sub.-- Out for every L clock cycles.
In the conventional synchronizing device constructed as stated above, the FIFO 153 requires a large storage capacity. This gives a obstacle in reducing the number of components forming the device for size reduction and manufacturing cost reduction of the device.